IBM Power Registers

Thanks to Srikar Dronamraju & Raghavendtra T Patel for providing details.

r1  stack pointer

r2 TOC (on 64 bit) Table of contents

r3..r9 are used to pass arguments

r3 to r12 are volatile registers.
LR Link Register

CR1 CR2 CR3 condition register.

r2 thread specific (32 bit)

r13 thread specific ( 64 bit)
r11-r12 functional link
r31 parameters

More Details:    http://www.ibm.com/developerworks/library/l-powasm4/